1. Field of the Invention
This invention relates to a semiconductor integrated circuit, for example, a logic circuit, exhibiting decreased leakage current and increased processing speed during operation under control of a state signal from a control circuit.
2. Discussion of Background
In recent years, semiconductor integrated circuits are used in various technical fields thanks to advances in semiconductor technology. But the semiconductor integrated circuit, for example a microprocessor which includes CMOS technology, has two important problems involving input power consumption and device speed. It is difficult to solve the two problems and achieve low input power consumption and high speed performance at the same time, for example, using CMOS technology.
Recently, MT-CMOS (Multi-Threshold CMOS) has been developed in an attempt to solve the two problems at the same time. FIG. 19 shows a circuit diagram of an MT-CMOS semiconductor integrated circuit which is used in a compact information terminal. The MT-CMOS integrated circuit includes a transistor having a high threshold voltage and a transistor having a low threshold voltage. In FIG. 19, the MT-CMOS semiconductor integrated circuit includes a p type MOS transistor Q1, an n type MOS transistor Q2, a potential line VDDV (hereinafter referred to as "VDDV"), a potential line GNDV (hereinafter referred to as "GNDV"), and a logic circuit 11 shown in dotted line. The transistors in the logic circuit have a low threshold voltage. The p type MOS transistor Q1 and the n type MOS transistor Q2 each have a high threshold voltage. VDDV is supplied with VDD via transistor Q1. GNDV is supplied with GND via transistor Q2. The logic circuit is composed of CMOS transistors powered by VDDV and GNDV. The gate of the p type MOS transistor Q1 is connected to a signal line SL, the source of the p type MOS transistor Q1 is supplied with VDD and the drain of the p type MOS transistor Q1 is connected to VDDV. The gate of the n type MOS transistor Q2 is connected to a signal line SL, the drain of the n type MOS transistor Q2 is supplied with GND and the source of the n type MOS transistor Q2 is connected to GNDV. The signal lines SL and SL are complementary digital signals.
When the level of the signal line SL is a high level ("H", e.g., VDD) and the level of the signal line SL is a low level ("L", e.g., GND), the logic circuit is non-conducting because both the p type MOS transistor Q1 and the n type MOS transistor Q2 are in the "OFF" state as the logic circuit 11 is not supplied with VDD and GND. This state is the standby state.
When the level of the signal line SL is "L" and the level of the signal line SL is "H", both the p type MOS transistor Q1 and the n type MOS transistor Q2 are "ON" and the logic circuit is supplied with VDD and GND. This state is the active state.
A threshold voltage of the p type MOS transistor Q1 is -0.5--0.7 V and a threshold voltage of the n type MOS transistor Q2 is 0.5-0.7 V. The threshold voltage of each p type MOS transistor and that of each n type MOS transistor in the logic circuit are -0.2--0.3 V and 0.2-0.3 V, respectively. Because the threshold voltages of the MOS transistors in the logic circuit 11 are low, the logic circuit 11 can perform logic functions at a low voltage (about 1 V) when in the active state. Because the threshold voltages of the p type MOS transistor Q1 and the n type MOS transistor Q2 are at a higher voltage than that of the transistors in the logic circuit, the leakage current is decreased when in the standby state.
Generally, when in the standby state, the leakage current (a subthreshold current) is generated in the MOS transistor. When the threshold voltage (Vth) decreases to 0.1 V, the leakage current increases at least 10 times. Therefore, in such a case, the leakage current of the MOS transistors having a low threshold voltage (in the logic circuit) becomes not less than 1,000 times that of the MOS transistors having a high threshold voltage (i.e., the p type MOS transistor Q1 and the n type MOS transistor Q2).
But, in FIG. 19, when in the standby state, the leakage current is not generated in the logic circuit, because the p type MOS transistor Q1 and the n type MOS transistor Q2 are turned OFF by the signals SL and SL. Thus, the semiconductor integrated circuit of FIG. 19 has only the leakage currents of the p type MOS transistor Q1 and the n type MOS transistor Q2 when in the standby state. Therefore, the input power consumption of the MT-CMOS logic circuit is low (1/1,000 or less than that without the MOS transistors Q1 and Q2 (n-MT-CMOS)), because the leakage current of the logic circuit is not generated when in the standby state.
FIG. 20 is a sectional view of a semiconductor chip to realize the CMOS transistor circuits. In FIG. 20, the semiconductor chip includes a silicon substrate 1 in which a p type well 2 and an n type well 3 are formed. A plurality of n type semiconductor regions 4a-4d are formed in the p type well 2, a plurality of p type semiconductor regions 5a-5d are formed in the n type well 3, a plurality of n type gate electrodes 6a-6c are formed on the p type well 2 through an insulating layer (not shown), a plurality of p type gate electrodes 7a-7c are formed on the n type well 3 through an insulating layer (not shown), an isolation layer 8 is formed to separate the p type well 2 and the n type well 3, a p type semiconductor region 9 have a higher impurity concentration than the rest of the well 2 is formed in the p type well 2, and an n type semiconductor region 10 have a higher impurity concentration than the rest of the well 3 is formed in the n type well 3.
The logic circuit 11 includes a transistor T1 which consists of the n type semiconductor regions 4b, 4c and the gate electrode 6b, an transistor T2 which consists of the n type semiconductor regions 4c, 4d and the gate electrode 6c, a transistor T3 which consists of the p type semiconductor regions 5c, 5d and the gate electrode 7b and a transistor T4 which consists of the p type semiconductor regions 5c, 5d and the gate electrode 7c. The p type MOS transistor Q1 consists of the p type semiconductor regions 5a, 5d and the gate electrode 7a. The n type MOS transistor Q2 consists of the n type semiconductor regions 4a, 4b and the gate electrode 6a. The gate electrode 7a and the gate electrode 6a are connected to the signal line SL and the signal line SL, respectively. The n type semiconductor region 10 and the p type semiconductor region 9 are formed with a higher impurity concentration to provide the p type MOS transistor Q1 and the n type MOS transistor Q2 with a higher threshold voltage compared to that of the transistors T1, T2, T3 and T4.
In the p type well 2, the n type semiconductor regions 4a, 4b, 4c, 4d are formed at the same time by the same doping process. After that process, the p type semiconductor region 9 is formed between n type semiconductor region 4a and n type semiconductor region 4b by ion implantation of aluminum ions or boron ions. Then, in the n type well 3, the p type semiconductor regions 5a, 5b, 5c, 5d are formed at the same time by the same doping process. After that process, the n type semiconductor region 10 is formed between the n type semiconductor region 5a and the n type semiconductor region 5b by ion implantation of phosphorus ions.
In the above semiconductor integrated circuit, a low input power consumption is desired. The threshold voltages (absolute value) of the p type MOS transistor Q1 and the n type MOS transistor Q2 are designed so as not to generate a large leakage current in the standby state between the power supply (VDD and GND) and the logic circuit 11.
However, it is difficult to obtain the desired threshold voltage by the impurity doping process at the present level of technical skill in semiconductor manufacturing. As a result, not only is low input power consumption not achieved, but also manufacturing yield decreases due to sub-standard MOS transistors.
Further, the provision of low voltage threshold MOS transistors and high voltage threshold MOS transistors on a common semiconductor substrate in the above semiconductor integrated circuit results in a complicated manufacturing process due to the extra doping steps required to dope an impurity in the channel region 9 of the p type MOS transistor Q1 and in the channel region 10 of the n type MOS transistor Q2, as well as the concomitant masks required to dope the impurities in the semiconductor integrated circuit. As a result, the manufacturing productivity is remarkably reduced.
Still further, it is not possible to ignore the ON resistance of the p type MOS transistor Q1 and that of the n type MOS transistor Q2 shown in FIG. 19. These ON resistances prevent high performance of the logic circuit. For example, even though the threshold voltage of the p type MOS transistor Q1 is reduced, or the threshold voltage of n type MOS transistor Q2 is increased, although the leakage current is thereby decreased, when the MOS transistors is in the ON state, the ability to drive the MOS transistors is prevented by such threshold voltages.